High-performance reconfigurable synaptic transistor enabled by coupled interface and ferroelectricity based on SnS₂/dual-Al₂O₃/Hf_0.5Zr_0.5O₂

With the rapid development of in-memory sensing and computing, ferroelectric field-effect transistors (Fe-FETs) have emerged as promising candidates in neuromorphic computing due to their simple structure, reliable programmability and low energy consumption. High-efficiency neuromorphic hardware system requires synaptic transistor to follow a linear/symmetric weight updating rule under control of a simple stimulus scheme. However, in most 2D Fe-FETs reported so far, achieving such linear and symmetric weight updates typically relies on an incremental stimulus scheme, which undoubtedly increase the hardware complexity and cost. Here, we demonstrate a reconfigurable SnS₂/dual-Al₂O₃/Hf_0.5Zr_0.5O₂ Fe-FET that exhibits robust multilevel conductance states with a good linearity/symmetry under equal electrical pulse stimuli. Moreover, the device integrates nonvolatile and volatile resistance modulation capabilities under light stimuli. The dual-Al₂O₃ capping layers and ferroelectric polarization of Hf_0.5Zr_0.5O₂ are identified as key factors enabling the rich conductance plasticity with flexible time dynamics. The device is applied in in-memory image processing, MNIST handwritten digits recognition and reservoir computing with high performance. Our work provides a novel strategy to design a charge trapping-involved ferroelectric field-effect transistor featuring both a linear weight updating and a wide tunable dynamics window, demonstrating significant potential in future high-performance and low-cost neuromorphic computing.